module stimulus;

   reg clk, reset;  // Always declared so can simulate based on clock
   integer     handle3;
   integer     desc3;   
   
   // Instantiate the design block counter
   sim12 dut (clk, reset);
   
   // Setup the clock to toggle every 1 time units 
  initial 
    begin	
	     clk = 1'b1;
	     forever #10 clk = ~clk;
    end
  
       // Stimulate the Input Signals
  initial
    begin
      // Add your test vectors here
      #0  reset = 1'b1;
      #5  reset = 1'b0;
    end
  
  always 
    begin
      desc3 = handle3;
      #5 $fdisplay(desc3, "%b",  reset); 
    end
       
  initial
     begin
	     // Gives output file name
	     handle3 = $fopen("tsimple12.out");
     end
  
endmodule // stimulus

